1. Field of the Invention
The present invention relates to a semiconductor light receiving element suitably applicable to optical communication and a method of manufacturing the same, and an optical communication system including the semiconductor light receiving element.
2. Description of the Related Art
In general, in a PIN photodiode (p-intrinsic-n photodiode) for optical communication, a columnar mesa is formed by stacking an n-type buffer layer, a light absorbing layer, and a p-type cap layer on an n-type semiconductor substrate, for example, as described in Japanese Unexamined Patent Publication No. Hei 1-239973. On the upper surface of the mesa, a ring-shaped upper electrode having an opening in a light incidence region is provided, and on the rear surface of the n-type semiconductor substrate, a lower electrode is provided. In a PIN photodiode having such a configuration, when light enters into the light incidence region on the condition that a reverse-bias voltage is applied between the upper electrode and the lower electrode, the light is converted into photocurrent in the light absorbing layer, and the converted photocurrent is outputted as an optical output signal from the upper electrode and the lower electrode.
To realize high-capacity communication in PIN photodiodes for optical communication, high-speed response is desired. The response speed is basically limited by CR time constant and travel time of carriers in the light absorbing layer. In the CR time constant, the light absorbing layer is preferably thick to reduce the capacity, but in the travel time of carriers, the light absorbing layer is preferably thin. To efficiently convert light entering to the light incidence region into photocurrent, an area in a stacking in-plane direction of the light absorbing layer is preferably large. In this case, however, it causes an increase in capacity. In other words, to realize the high-speed response, it is necessary to optimize these parameters.
In Japanese Unexamined Patent Publication No. Hei 1-239973, measures are indicated that, to improve CR time constant, a low dielectric constant layer is provided adjacent to a mesa, and an extraction electrode connected to an upper electrode on the upper surface of the mesa is formed on the upper surface of the low dielectric constant layer, thereby reducing capacity between the extraction electrode and a lower electrode. In Japanese Patent No. 3183931, measures are indicated that a buffer layer is lightly-doped, thereby reducing capacity between an upper electrode and a lower electrode.